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Host Programmer Model
7
6
5
4
3
2
1
0
INIT
HLEND
HF1
HF0
HDRQ TREQ RREQ
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-15. Interface Control Register (ICR)
Table 6-15. Interface Control Register (ICR) Bit Definitions
Bit Number
7
Bit Name
INIT
Reset Value
0
Initialize
Description
The host processor uses INIT to force initialization of the HI08 hardware.
During initialization, the HI08 transmit and receive control bits are configured.
Use of the INIT bit to initialize the HI08 hardware depends on the software
design of the interface. The type of initialization when the INIT bit is set
depends on the state of TREQ and RREQ The INIT command, which is local
to the HI08, configures the HI08 into the desired data transfer mode. When
the host sets the INIT bit, the HI08 hardware executes the INIT command.
The interface hardware clears the INIT bit after the command executes.
TREQ
0
0
RREQ
0
1
After INIT Execution
INIT = 0
INIT = 0;
Transfer Direction
None
DSP to host
RXDF = 0; HTDE = 1
1
0
INIT = 0;
Host to DSP
TXDE = 1; HRDF = 0
1
1
INIT = 0;
Host to/from DSP
RXDF = 0; HTDE = 1;
TXDE = 1; HRDF = 0
6
0
Reserved. Write to 0 for future compatibility.
5
HLEND
0
Host Little Endian
If the HLEND bit is cleared, the host can access the HI08 in Big-Endian byte
order. If set, the host can access the HI08 in Little-Endian byte order. If the
HLEND bit is cleared the RXH/TXH register is located at address $5, the
RXM/TXM register at $6, and the RXL/TXL register at $7. If the HLEND bit is
set, the RXH/TXH register is located at address $7, the RXM/TXM register at
$6, and the RXL/TXL register at $5.
4
HF1
0
Host Flag 1
A general-purpose flag for host-to-DSP communication. The host processor
can set or clear HF1, and the DSP56311 can not change it. HF1 is reflected
in the HSR on the DSP side of the HI08.
3
HF0
0
Host Flag 0
A general-purpose flag for host-to-DSP communication. The host processor
can set or clear HF0, and the DSP56311 cannot change it. HF0 is reflected in
the HSR on the DSP side of the HI08.
2
HDRQ
0
Double Host Request
If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as
HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is configured
as HTRQ, and HACK/HRRQ is configured as HRRQ.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
6-23
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